/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __CLK_IMX_IMX6QDL_H
#define __CLK_IMX_IMX6QDL_H

#define IMX6QDL_CLK_DUMMY			0
#define IMX6QDL_CLK_CKIL			1
#define IMX6QDL_CLK_CKIH			2
#define IMX6QDL_CLK_OSC				3
#define IMX6QDL_CLK_PLL2_PFD0_352M		4
#define IMX6QDL_CLK_PLL2_PFD1_594M		5
#define IMX6QDL_CLK_PLL2_PFD2_396M		6
#define IMX6QDL_CLK_PLL3_PFD0_720M		7
#define IMX6QDL_CLK_PLL3_PFD1_540M		8
#define IMX6QDL_CLK_PLL3_PFD2_508M		9
#define IMX6QDL_CLK_PLL3_PFD3_454M		10
#define IMX6QDL_CLK_PLL2_198M			11
#define IMX6QDL_CLK_PLL3_120M			12
#define IMX6QDL_CLK_PLL3_80M			13
#define IMX6QDL_CLK_PLL3_60M			14
#define IMX6QDL_CLK_TWD				15
#define IMX6QDL_CLK_STEP			16
#define IMX6QDL_CLK_PLL1_SW			17
#define IMX6QDL_CLK_PERIPH_PRE			18
#define IMX6QDL_CLK_PERIPH2_PRE			19
#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
#define IMX6QDL_CLK_AXI_SEL			22
#define IMX6QDL_CLK_ESAI_SEL			23
#define IMX6QDL_CLK_ASRC_SEL			24
#define IMX6QDL_CLK_SPDIF_SEL			25
#define IMX6QDL_CLK_GPU2D_AXI			26
#define IMX6QDL_CLK_GPU3D_AXI			27
#define IMX6QDL_CLK_GPU2D_CORE_SEL		28
#define IMX6QDL_CLK_GPU3D_CORE_SEL		29
#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
#define IMX6QDL_CLK_IPU1_SEL			31
#define IMX6QDL_CLK_IPU2_SEL			32
#define IMX6QDL_CLK_LDB_DI0_SEL			33
#define IMX6QDL_CLK_LDB_DI1_SEL			34
#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
#define IMX6QDL_CLK_IPU1_DI0_SEL		39
#define IMX6QDL_CLK_IPU1_DI1_SEL		40
#define IMX6QDL_CLK_IPU2_DI0_SEL		41
#define IMX6QDL_CLK_IPU2_DI1_SEL		42
#define IMX6QDL_CLK_HSI_TX_SEL			43
#define IMX6QDL_CLK_PCIE_AXI_SEL		44
#define IMX6QDL_CLK_SSI1_SEL			45
#define IMX6QDL_CLK_SSI2_SEL			46
#define IMX6QDL_CLK_SSI3_SEL			47
#define IMX6QDL_CLK_USDHC1_SEL			48
#define IMX6QDL_CLK_USDHC2_SEL			49
#define IMX6QDL_CLK_USDHC3_SEL			50
#define IMX6QDL_CLK_USDHC4_SEL			51
#define IMX6QDL_CLK_ENFC_SEL			52
#define IMX6QDL_CLK_EMI_SEL			53
#define IMX6QDL_CLK_EMI_SLOW_SEL		54
#define IMX6QDL_CLK_VDO_AXI_SEL			55
#define IMX6QDL_CLK_VPU_AXI_SEL			56
#define IMX6QDL_CLK_CKO1_SEL			57
#define IMX6QDL_CLK_PERIPH			58
#define IMX6QDL_CLK_PERIPH2			59
#define IMX6QDL_CLK_PERIPH_CLK2			60
#define IMX6QDL_CLK_PERIPH2_CLK2		61
#define IMX6QDL_CLK_IPG				62
#define IMX6QDL_CLK_IPG_PER			63
#define IMX6QDL_CLK_ESAI_PRED			64
#define IMX6QDL_CLK_ESAI_PODF			65
#define IMX6QDL_CLK_ASRC_PRED			66
#define IMX6QDL_CLK_ASRC_PODF			67
#define IMX6QDL_CLK_SPDIF_PRED			68
#define IMX6QDL_CLK_SPDIF_PODF			69
#define IMX6QDL_CLK_CAN_ROOT			70
#define IMX6QDL_CLK_ECSPI_ROOT			71
#define IMX6QDL_CLK_GPU2D_CORE_PODF		72
#define IMX6QDL_CLK_GPU3D_CORE_PODF		73
#define IMX6QDL_CLK_GPU3D_SHADER		74
#define IMX6QDL_CLK_IPU1_PODF			75
#define IMX6QDL_CLK_IPU2_PODF			76
#define IMX6QDL_CLK_LDB_DI0_PODF		77
#define IMX6QDL_CLK_LDB_DI1_PODF		78
#define IMX6QDL_CLK_IPU1_DI0_PRE		79
#define IMX6QDL_CLK_IPU1_DI1_PRE		80
#define IMX6QDL_CLK_IPU2_DI0_PRE		81
#define IMX6QDL_CLK_IPU2_DI1_PRE		82
#define IMX6QDL_CLK_HSI_TX_PODF			83
#define IMX6QDL_CLK_SSI1_PRED			84
#define IMX6QDL_CLK_SSI1_PODF			85
#define IMX6QDL_CLK_SSI2_PRED			86
#define IMX6QDL_CLK_SSI2_PODF			87
#define IMX6QDL_CLK_SSI3_PRED			88
#define IMX6QDL_CLK_SSI3_PODF			89
#define IMX6QDL_CLK_UART_SERIAL_PODF		90
#define IMX6QDL_CLK_USDHC1_PODF			91
#define IMX6QDL_CLK_USDHC2_PODF			92
#define IMX6QDL_CLK_USDHC3_PODF			93
#define IMX6QDL_CLK_USDHC4_PODF			94
#define IMX6QDL_CLK_ENFC_PRED			95
#define IMX6QDL_CLK_ENFC_PODF			96
#define IMX6QDL_CLK_EMI_PODF			97
#define IMX6QDL_CLK_EMI_SLOW_PODF		98
#define IMX6QDL_CLK_VPU_AXI_PODF		99
#define IMX6QDL_CLK_CKO1_PODF			100
#define IMX6QDL_CLK_AXI				101
#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
#define IMX6QDL_CLK_ARM				104
#define IMX6QDL_CLK_AHB				105
#define IMX6QDL_CLK_APBH_DMA			106
#define IMX6QDL_CLK_ASRC			107
#define IMX6QDL_CLK_CAN1_IPG			108
#define IMX6QDL_CLK_CAN1_SERIAL			109
#define IMX6QDL_CLK_CAN2_IPG			110
#define IMX6QDL_CLK_CAN2_SERIAL			111
#define IMX6QDL_CLK_ECSPI1			112
#define IMX6QDL_CLK_ECSPI2			113
#define IMX6QDL_CLK_ECSPI3			114
#define IMX6QDL_CLK_ECSPI4			115
#define IMX6Q_CLK_ECSPI5			116
#define IMX6DL_CLK_I2C4				117
#define IMX6QDL_CLK_ENET			118
#define IMX6QDL_CLK_ESAI_EXTAL			119
#define IMX6QDL_CLK_GPT_IPG			120
#define IMX6QDL_CLK_GPT_IPG_PER			121
#define IMX6QDL_CLK_GPU2D_CORE			122
#define IMX6QDL_CLK_GPU3D_CORE			123
#define IMX6QDL_CLK_HDMI_IAHB			124
#define IMX6QDL_CLK_HDMI_ISFR			125
#define IMX6QDL_CLK_I2C1			126
#define IMX6QDL_CLK_I2C2			127
#define IMX6QDL_CLK_I2C3			128
#define IMX6QDL_CLK_IIM				129
#define IMX6QDL_CLK_ENFC			130
#define IMX6QDL_CLK_IPU1			131
#define IMX6QDL_CLK_IPU1_DI0			132
#define IMX6QDL_CLK_IPU1_DI1			133
#define IMX6QDL_CLK_IPU2			134
#define IMX6QDL_CLK_IPU2_DI0			135
#define IMX6QDL_CLK_LDB_DI0			136
#define IMX6QDL_CLK_LDB_DI1			137
#define IMX6QDL_CLK_IPU2_DI1			138
#define IMX6QDL_CLK_HSI_TX			139
#define IMX6QDL_CLK_MLB				140
#define IMX6QDL_CLK_MMDC_CH0_AXI		141
#define IMX6QDL_CLK_MMDC_CH1_AXI		142
#define IMX6QDL_CLK_OCRAM			143
#define IMX6QDL_CLK_OPENVG_AXI			144
#define IMX6QDL_CLK_PCIE_AXI			145
#define IMX6QDL_CLK_PWM1			146
#define IMX6QDL_CLK_PWM2			147
#define IMX6QDL_CLK_PWM3			148
#define IMX6QDL_CLK_PWM4			149
#define IMX6QDL_CLK_PER1_BCH			150
#define IMX6QDL_CLK_GPMI_BCH_APB		151
#define IMX6QDL_CLK_GPMI_BCH			152
#define IMX6QDL_CLK_GPMI_IO			153
#define IMX6QDL_CLK_GPMI_APB			154
#define IMX6QDL_CLK_SATA			155
#define IMX6QDL_CLK_SDMA			156
#define IMX6QDL_CLK_SPBA			157
#define IMX6QDL_CLK_SSI1			158
#define IMX6QDL_CLK_SSI2			159
#define IMX6QDL_CLK_SSI3			160
#define IMX6QDL_CLK_UART_IPG			161
#define IMX6QDL_CLK_UART_SERIAL			162
#define IMX6QDL_CLK_USBOH3			163
#define IMX6QDL_CLK_USDHC1			164
#define IMX6QDL_CLK_USDHC2			165
#define IMX6QDL_CLK_USDHC3			166
#define IMX6QDL_CLK_USDHC4			167
#define IMX6QDL_CLK_VDO_AXI			168
#define IMX6QDL_CLK_VPU_AXI			169
#define IMX6QDL_CLK_CKO1			170
#define IMX6QDL_CLK_PLL1_SYS			171
#define IMX6QDL_CLK_PLL2_BUS			172
#define IMX6QDL_CLK_PLL3_USB_OTG		173
#define IMX6QDL_CLK_PLL4_AUDIO			174
#define IMX6QDL_CLK_PLL5_VIDEO			175
#define IMX6QDL_CLK_PLL8_MLB			176
#define IMX6QDL_CLK_PLL7_USB_HOST		177
#define IMX6QDL_CLK_PLL6_ENET			178
#define IMX6QDL_CLK_SSI1_IPG			179
#define IMX6QDL_CLK_SSI2_IPG			180
#define IMX6QDL_CLK_SSI3_IPG			181
#define IMX6QDL_CLK_ROM				182
#define IMX6QDL_CLK_USBPHY1			183
#define IMX6QDL_CLK_USBPHY2			184
#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		185
#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		186
#define IMX6QDL_CLK_SATA_REF			187
#define IMX6QDL_CLK_SATA_REF_100M		188
#define IMX6QDL_CLK_PCIE_REF			189
#define IMX6QDL_CLK_PCIE_REF_125M		190
#define IMX6QDL_CLK_ENET_REF			191
#define IMX6QDL_CLK_USBPHY1_GATE		192
#define IMX6QDL_CLK_USBPHY2_GATE		193
#define IMX6QDL_CLK_PLL4_POST_DIV		194
#define IMX6QDL_CLK_PLL5_POST_DIV		195
#define IMX6QDL_CLK_PLL5_VIDEO_DIV		196
#define IMX6QDL_CLK_EIM_SLOW			197
#define IMX6QDL_CLK_SPDIF			198
#define IMX6QDL_CLK_CKO2_SEL			199
#define IMX6QDL_CLK_CKO2_PODF			200
#define IMX6QDL_CLK_CKO2			201
#define IMX6QDL_CLK_CKO				202
#define IMX6QDL_CLK_VDOA			203
#define IMX6QDL_CLK_PLL4_AUDIO_DIV		204
#define IMX6QDL_CLK_LVDS1_SEL			205
#define IMX6QDL_CLK_LVDS2_SEL			206
#define IMX6QDL_CLK_LVDS1_GATE			207
#define IMX6QDL_CLK_LVDS2_GATE			208
#define IMX6QDL_CLK_ESAI_IPG			209
#define IMX6QDL_CLK_ESAI_MEM			210
#define IMX6QDL_CLK_ASRC_IPG			211
#define IMX6QDL_CLK_ASRC_MEM			212
#define IMX6QDL_CLK_END				213

#endif /* __CLK_IMX_IMX6QDL_H */
